1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices and, in particular, to the identification of failures in a metrology tool used to measure dimensions in microelectronic features.
2. Description of Related Art
During microelectronics manufacturing, a semiconductor wafer is processed through a series of tools that perform lithographic processing to form features and devices that form the microelectronic circuits and other features on the substrate of the wafer. Lithographic systems replicate circuit patterns by projecting the image of a mask pattern onto a wafer, and consist of imaging tools that expose patterns and processing tools that coat, bake and develop the substrates. The pattern may consist of features of varying size and density, all of which must be printed simultaneously with dimensional fidelity to design. As used herein, the term critical dimension (CD) or critical width refers to the smallest dimension of a pattern or feature that can be produced by the lithographic system. Such processing has a broad range of industrial applications, including the manufacture of semiconductors, flat-panel displays, micromachines, and disk heads.
Generally after each process step, any errors on the wafer are measured and controlled using metrology tools that image dimensions either on portions of the microelectronic circuits themselves or on specialized targets printed on the wafer. Such circuit portions, targets, and other features shall be generally referred to as microelectronic features, unless otherwise specified. The metrology tools use so-called recipes to make measurements of desired microelectronic features. Such recipes generally comprise maps of the microelectronic features and commands to the tools optical measurement systems to align the particular feature to be measured with the tool measurement device, by rotation and translation of the wafer with respect to the tool, and to use the required tool measurement device. A typical tool measurement device may use purely optical schemes to obtain the respective measurements, examples of these types of tools include overlay, scatterometry and film thickness. Other tool measurement devices include an optical device in conjunction with a scanning electron, atomic force microscopy or some other combination where each tool measurement device is designed to measure specific process steps along the way during chip fabrication. From this point forward measuring a desired dimension of a microelectronic feature can mean measuring critical dimensions, overlay, film thickness, depth and the like.
As metrology tools become more and more advanced, they require more skill on the part of the user. The experience needed to create measurement recipes is quickly becoming out of the reach of the average user. Additionally, the number of process steps being measured on metrology tools is growing with each new generation chip process. For 65 nm node chip technology, the chip may pass through a critical dimension (CD) metrology tool about 70 times in the course of its processing. Each of those 70 passes requires a unique recipe to be constructed. Many times dozens of different types of chips are being created using the 65 nm node chip technology, with each of the same process steps for each unique chip requiring a unique metrology recipe. Such CD metrology recipes can easily number in the thousands.
Knowing that a high level of expertise is needed to create a robust recipe, many chip fabricators do not have sufficient manpower to allow all of these thousands of recipes to be created as robustly as needed. In many cases the recipes created do not run robustly. Over time this becomes a significant issue that directly affects the cycle time needed to build a fully functioning chip; in some extreme cases it affects yield. Since it could take a year or more to master programming recipes on some metrology tools, poorly written metrology recipes create major problems in metrology tool management, cycle time and process debug.
With the thousands of recipes that exist on metrology tools used to monitor the processes in making chips, there is a need for effective way of determining which recipes are most problematic. Further, there are many opportunities for a production lot at a particular process step to fail using the metrology recipe created to monitor that process step. Given that a chip fabricator may have a dozen or more CD tools measuring all the different chips at different process steps during their lifetime, coupled with many poorly written recipes, the amount of recipe failures could reach levels in the tens of thousands within a fairly short time period. A recipe failure may pause the metrology tool, resulting in a lot that did not measure robustly to go on hold and require investigation. This and other situations can, in turn, slow down the chip construction and directly impact the cycle time. Without an effective way of determining the problematic recipe, much time and resources may be wasted.